1. Field of the Invention
The invention relates in general to a method of fabricating a memory device. More particularly, the invention relates to a method of fabricating a random access memory (SRAM).
2. Description of the Related Art
A static random access memory is a kind of semiconductor memory with a very high processing speed. In the typical design, a static random access memory comprises four transistors and two resistors (4T2R) or six transistors (6T). According to the demands of low power/low voltage, the static random access memory with six transistors is more stable.
According to the different functions, the static random access memory comprises different memory cells such as pull down device (PD), P type load device (PMOS load device, PL) and pass gate device (PG). The circuit structure is shown as FIG. 1. As the dimension of the device shrinks, the stability becomes more important while the operation voltage of the memory cell in the static random access memory is dropped lower than 1.8 V.
Generally speaking, when the cell ratio of current between the pull down device and pass gate device is larger, the stability of the memory cell is higher. The typical memory cell fabrication method enhances the stability by increasing the current of the pull down device. However, to increase the operation speed of devices, the current of the pass gate device has to be increased. Consequently, the cell ratio is decreased, and the stability of the devices is lowered. Therefore, there is a tradeoff between the enhancement of the stability and the operation speed.
The method of fabricating a conventional static random access memory is shown as FIGS. 2, 3 and 4. FIG. 3 is a cross sectional view cutting along the line III--III of FIG. 2, while FIG. 4 is a cross sectional view cutting along the line IV--IV. The conventional method includes forming the stacked gate of a pull down device, a PMOS load device, and a gate pass device 204, a lightly doped drain/source region 206, and a spacer 208 on each sidewall of the stacked gate 204 after an active region 202 is defined. A heavily doped ion implantation is performed, followed by a self-align silicide process to form a heavily doped drain/source region and metal silicide layers 210 and 212 thereon. A contact window 214 is then formed, and the following metallization process is performed.
As the spacer 208 has a significant thickness, the lightly doped source region 206 between the stacked gates of two neighboring memory cells 204a and 204b is covered with the spacer 208 as shown in FIG. 3. Only a predetermined contact window region 216 of the lightly doped source region 206 is exposed, as shown in FIG. 4. Thus, in the subsequent processes of heavily doped ion implantation and self-align silicidation, the heavily doped source region and the metal silicide layer are formed only on the contact region 216. No heavily doped source region and metal silicide layer will be formed on the non-contact region 218.
When the current flows from the drain region of the pull down device through the source region of the non-contact region 218, being blocked by the spacer 208, the source region comprises only the lightly doped source region. Therefore, a very high resistance is incurred.
In addition, while forming a contact window 214 to connect a ground voltage Vss on the lightly doped source region 206, once misalignment occurs, the contact window 214 shifts towards the non-contact region 218, to partly be on the spacer 208 on the non-contact region 218. As a result, the contact area between the contact window 214 and the contact region 216 is decreased, so that the resistance of the source region is greatly increased.
The above conventional method for fabricating the static random access memory increases the resistance of the source region. Consequently, the current of the pull down device is reduced to reduce the cell ratio. The stability of the static random access memory is thus greatly affected.